Thông báo tuyển dụng Thực tập thực tế tại Intel Vietnam

Vị trí tuyển dụng:
· Physical design (Automatic Place and Route)
· Static Timing Analysis (STA)
Đối tượng: Ưu tiên SV năm 4.
Mô tả công việc:
Job description:
Your responsibilities will include but not be limited to:
– Block-level floor planning
– Logic synthesis of design blocks
– Exploring new AI tools or flows to aid in SOC convergence
– Formal Equivalence Verification (FEV), Auto Place-and-Route (APR) using Synopsys ICC tools
– Timing verification using Synopsys Prime Time
– Layout vs. Schematic LVS, Design Rule Checks DRC, Electrical Rule Checks ERC, and Design for Test
– Manufacturability checks DFM
– Assist in the preparation of the layout design database for introduction to manufacturing
– Participate in the design and development of AI enabling SOCs
In addition to the qualifications listed below, the ideal candidate will also have the following:
– Excellent communication skills
– Teamwork
– Strong analytical and problem-solving skills
– Willingness to work independently and at various levels of abstraction
– Interest and knowledge in AI and machine learning technologies
Thời gian nộp CV: từ 20/2/2024 – 20/3/2024
Địa chỉ nộp: ; Mr. Nguyễn Minh Tuấn